The present invention is directed to depositing a layer containing Al, N, and Si upon a substrate by chemical vapor deposition and articles obtained thereby. Moreover, the present invention is directed to preparing semiconductor devices such as MISFET devices including MOSFET and MIOSFET devices containing a layer comprising Al, N, and Si deposited upon a semiconductor substrate.
The materials which are presently utilized commercially for MOS (metal-oxide-semiconductor) and MIOS (metal-insulator-oxide-semiconductor) charge storage devices operated as field effect transistors within memory systems include silicon nitride (Si.sub.3 N.sub.4) or aluminum oxide (Al.sub.2 O.sub.3) for the charge storage layers as exemplified by D. Frohman et al, Proceedings IEEE, Vol. 58, No. 8, August 1970; M. White et al, IEEE Transactions, Electrochemical Division, Vol. ED-19, No. 12, December 1972; C. Nabor et al, Semiconductor Silicon, 1973 Edition, Electrochemical Society, Princeton, New Jersey; C. Salama, Journal Electrochemical Society, Vol. 117, No. 7, p. 913 (July 1970); and Balk et al, Journal Electrochemical Society, Vol. 118, p. 1634 (1971).
The above insulating materials have been widely used since they possess various favorable electrical properties which are required for acceptable charge storage devices such as large forbidden conduction band gaps, high dielectric constant, high DC resistance and breakdown voltage, and availability of energy traps within the forbidden band gap for charge storage. These electrical properties are important for such devices as read only or read mostly memories which require the ability to retain charges for relatively long periods of time such as several years and be electrically alterable with practical voltage pulse levels which are consistent with current computer electrical power systems.
However, the use of Si.sub.3 N.sub.4 and Al.sub.2 O.sub.3 has been somewhat restricted due to problems associated with the erasure of previously injected charges by reverse biasing. Although Al.sub.2 O.sub.3 can be electrically "written" at relatively low voltages such as from about 15 to about 25 v., erasure to the original state requires voltage pulses up to about 35 v. The application of large numbers of write and erase (charging and discharging) pulse cycles due to the high erasure voltage tends to result in early device failure. Additionally, Si.sub.3 N.sub.4 requires voltage pulses above 25 v. for both write and erase to obtain useful charge windows.
Accordingly, it is an object of the present invention to provide a method which makes it possible to prepare semiconductor devices which have improved ease of erasure properties for use as electrically alterable write-erase voltage window.
In addition, it is an object of the present invention to provide a method whereby it is possible to obtain semiconductor devices which possess reduced voltage requirements for maintaining stable memory voltage window.
Another property necessary for long term memory utilization is the capability of the particular device to retain the charge state previously written for the desired long period of time which is usually several years. It has been established both experimentally and theoretically that the written charge state constantly leaks its electrical charge at rates determined by the silicon oxide thickness, the amount of charge injected into the charge storage layer, and the particular electronic properties of the charge storage layer established by the chemical composition of the charge storage layer materials. For instance, see S. Zirinsky, "Charge Transfer Properties of MNOS Structures as Influenced by Processing Parameters", AIME, Electronic Materials Division Meeting, Boston, Massachusetts, Paper No. C3, September 1974, Journal of Electronic Materials, Plenum Press, New York, June 1975, Vol. 4, No. 3, p. 591, and L. Lundkvist et al, Solid State Electronics, Vol. 16, p. 811 (1973).
One method for designating the memory retention behavior of a particular device is the specification of rate of charge loss per decade of time (volts per decade of time) after initial charging to a specified charge level (volts initial). Both Al.sub.2 O.sub.3 and Si.sub.3 N.sub.4 show a linear loss rate per decade of time with the charge loss generally starting at approximately one millisecond following application of the writing pulse.
When writing initially to the range of +4 to +5 volts for the initial charge level, the charge level would discharge at a rate between 0.25 to 0.35 volts per decade of time. After periods between 1 and 10 years (10 to 11 decades of time), the final charge level will range between 1 and 1.5 volts, which is not considered acceptable for memory design considerations. Writing to higher charge levels does not solve this problem since larger charge loss rates are observed eventually yielding the same charge level for the period of time as obtained above. Lower charge loss rates can only be obtained with relative thickening of the oxide layer. However, this in turn necessitates the use of excessively high writing voltages that cause early multiple cycling device failure.
Accordingly, it is an object of the present invention to provide a method whereby the final charge level can be increased as compared to the values observed for the Si.sub.3 N.sub.4 or Al.sub.2 O.sub.3 layers.
A further object of the present invention is to provide a method whereby the composition of the film deposited on the substrate can be selectively controlled so that the desirable properties discussed hereinabove can be achieved. A further object of the present invention is to provide a method and article obtained thereby wherein the composition of the film is predictable and reproducible.